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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28823-2E
ASSP Image Control
CMOS
Intelligent On-screen Display Controller (IOSDC)
MB90091A
s DESCRIPTION
The MB90091A is the multisync, on-screen display controller that supports a variety of TV systems such as NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, and 1125HDTV as well as personal computer monitor display systems such as VGA and XGA. The MB90091A contains display memory (VRAM) and character font ROM, allowing characters to be displayed with few external devices. The device also contains command table ROM storing display command data, minimizing the load on the microcomputer. The on-screen display configuration is up to 24 characters x 12 lines, with each character consisting of 24 x 32 dots. The font ROM integrates 512 different character patterns. The character signal output is an RGB1 digital output. The display color of each character can be specified from among 16 colors. A color/monochrome select signal output is also provided for display either in 16 different colors or in 16-level gray scale. The character display functions include character background display, shaded background display, and sprite character display functions, contributing to providing colorful display screens.
s PACKAGES
64 pin, Plastic SH-DIP 64 pin, Plastic QFP
(DIP-64P-M01)
(FPT-64P-M06)
MB90091A
s FEATURES
* Screen display capacity * Font size * Font types : Up to 24 characters x 12 lines (288 characters) : 24 x 32 dots (horizontal x vertical) : 512 different characters (character codes 000H to 1FFH) 8 different sprite characters (character codes 1F8H to 1FFH) (Internal or external ROM selectable) : Trimmed display (pattern background 0, 1, or none) Character background (settable for each character) Shaded background (settable for each character) : Capable of displaying one character (selectable from among 8 types of characters) on the screen Sprite character colors : 8 colors Sprite trimming colors : 8 colors Sprite display position : Settable in 2-dot units on the screen : Normal, double width, double height, double width x double height, quadruple width, quadruple width x double height (Set for each line) : Character color Trimmed background color Character background color Screen background color : : : : 16 colors (set for each character) 16 colors (set for each line) 16 colors (set for each character) 16 colors
* Display modes
* Sprite character display
* Character sizes
* Display colors
* Display position control
: Horizontal display start position : Set in 8-dot units Vertical display start position : Set in 2-dot units Line spacing control : Set in 2-dot units (0 to 30 dots)
* Character/color signal output : ROUT, GOUT, BOUT, IOUT (color signals) COLOR (color/monochrome control signal) VOB1 (character + pattern background + character background + screen background: all-output signal) VOB2 (character + pattern background + character background: specifiedcharacter output signal) * Supported TV systems : NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, 1125HDTV, etc. Personal computer monitor display systems such as VGA : Automatic control of operation using on command table ROM Command table ROM: Internal 32K bytes + external 32K bytes available
* Intelligent features
* Microcontroller/microcomputer interface : 8-bit serial input (3 signal input pins Chip select: SCS Serial clock: SCLK Serial data: SIN * Package * Miscellaneous : SH-DIP-64, QFP-64 : Power-on reset circuit integrated
2
MB90091A
s PIN ASSIGNMENTS
(TOP VIEW)
COLOR DOCK V SS TESTCK TESTSW HBLNK VBLNK HSYNC VSYNC EVEN FLTIN AV SS FLTOUT AV CC FH RESET V CC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 TEST V SS TA16 TA17 TA18 FCS TCS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VOB2 VOB1 IOUT BOUT GOUT ROUT TRE V CC SCS SIN SCLK FSEL TSEL RA15 RA14 RA13 RA12 V SS RA11 RA10 RA9 RA8 RA7 RA6 RA5 V SS RA4 V CC RA3 RA2 RA1 RA0
(SH-DIP-64P)
(Continued)
3
MB90091A
(Continued)
(TOP VIEW)
VBLNK HBLNK TESTSW TESTCK V SS DOCK COLOR VOB2 VOB1 IOUT BOUT GOUT ROUT HSYNC VSYNC EVEN FLTIN AV SS FLTOUT AV CC FH RESET V CC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 TEST 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TRE V CC SCS SIN SCLK FSEL TSEL RA15 RA14 RA13 RA12 V SS RA11 RA10 RA9 RA8 RA7 RA6 RA5
4
V SS TA16 TA17 TA18 FCS TCS RA0 RA1 RA2 RA3 V CC RA4 V SS
(FPT-64P-M06)
MB90091A
s PIN DESCRIPTION
Pin No. DIP 8 9 QFP 1 2 Pin name HSYNC VSYNC I/O I I Function Horizontal sync signal input pin Dot clock generation is based on the cycle of the signal. Vertical sync signal input pin Field control signal input pin Input of an "L" level signal to this pin causes the font ROM address LSB pin (RA0) to output an "L" level signal. Input of an "H" level signal to this pin causes the font ROM address LSB pin (RA0) to output an "H" level signal (when normal-size characters are displayed). This pin is disabled in noninterlaced mode. Output pin for horizontal-sync phase comparison result signal This pin is connected to an external lowpass filter. Internal VCO voltage input pin This pin inputs the voltage signal from the external lowpass filter. Output pin for AFC-generated horizontal sync signal Reset pin This pin is enabled after release from a power-on reset.
10
3
EVEN
I
11 13 15 16 18 19 20 21 22 23 24 25 26 28 29 30 31 32
4 6 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25
FLTIN FLTOUT FH RESET RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 TEST TA16 TA17 TA18 FCS TCS
O I O I
I
External ROM data input pin This pin inputs data from external font ROM or external command data ROM.
I O O O
Test signal input pin This pin inputs an "L" level (fixed) signal during normal operation. Test signal output pin External font ROM chip select pin Chip select pin for external command table ROM
(Continued)
5
MB90091A
(Continued) Pin No.
DIP 33 34 35 36 38 40 41 42 43 44 45 46 48 49 50 51 QFP 26 27 28 29 31 33 34 35 36 37 38 39 41 42 43 44
Pin name RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15
I/O
Function
External ROM address signal output pin This pin outputs the signal specifying the external font ROM or external command table ROM address. External font ROM addresses RA0 to RA4 : Raster addresses RA5 to RA11 : Character codes (M0 to M6) RA12, RA13 : Character horizontal address = (0, 0): Left byte = (1, 0): Center byte = (0, 1): Right byte RA14, RA15 : Character codes (M7, M8)
O
52
45
TSEL
I
Address control input pin for command table ROM "L" level input : 0000H to 7FFFH Internal ROM 8000H to FFFFH External ROM "H" level input : 0000H to 7FFFH External ROM 8000H to FFFFH Internal ROM Internal/external font ROM select pin "L" level input : Select internal ROM. "H" level input : Select external ROM. Shift clock input pin for serial transfer Serial data input pin Chip select pin For serial transfer, set this pin to the "L" level. This pin is also used to cancel a power-on reset. Output pin for the signal indicating internal operation This pin outputs an "H" level signal during data transfer from command table ROM. Chrominance signal output pin For output of a character, character background, pattern background, shaded background, screen background, or sprite character (including a pattern background), this pin outputs the chrominance signal. Pin for specifying the chrominance signal output period This pin outputs an "H" level signal for output of a character, character background, pattern background, shaded background, screen background, or sprite character (including a pattern background. Pin for specifying the specified character output period When the command 6: ATH bit = "1", this pin outputs an "H" level signal in the character output period (24 x 32 dot period) when the command 1: AT bit = "1". The pin can be used for display control by an external circuit, for example, for halftone display control.
53 54 55 56
46 47 48 49
FSEL SCLK SIN SCS
I I I I
58 59 60 61 62
51 52 53 54 55
TRE ROUT GOUT BOUT IOUT
O
O
63
56
VOB1
O
64
57
VOB2
O
(Continued)
6
MB90091A
(Continued) Pin No.
DIP QFP
Pin name
I/O
Function Color/monochrome select signal output pin This pin allows "H" or "L" level output in each of the character, character background, line background, screen background, and sprite output periods to be specified depending on the internal register setting. Color/monochrome display is controlled by an external circuit. (The following correspondence is used for convenience: "L" level: Monochrome display "H" level: Color display) Dot clock output pin This pin outputs a dot clock signal when the command 11:DOT = "1". Test signal input pin This pin inputs an "H" level (fixed) signal during normal operation. Test signal input pin This pin inputs an "H" level (fixed) signal during normal operation. Horizontal blanking signal input pin This pin stops display signal output ("L" level output) when it inputs an "L" level signal. Vertical blanking signal input pin This pin stops display signal output ("L" level output) when it inputs an "L" level signal. +5 V power supply pin
1
58
COLOR
O
2 4 5 6
59 61 62 63
DOCK TESTCK TESTSW HBLNK
O I I I
7 17 37 57 27 39 47 3 14 12
64 10 30 50 20 32 40 60 7 5
VBLNK
I
VCC
--
VSS AVCC AVSS
-- -- --
Ground pin +5V power supply pin for VCO Ground pin for VCO
7
MB90091A
s BLOCK DIAGRAM
MB90091A
SCS SIN SCLK
TRE TSEL Serial input control Command table ROM control TCS RA0 to 15 RD0 to 7
Command table ROM
FLTIN LPF FLTOUT Dot clock generator
FH
Command table ROM
DOCK
FCS HSYNC VSYNC EVEN Display memory control
Font ROM Font ROM control
FSEL
Display memory (VRAM)
Font ROM
Display data output control
BOUT ROUT GOUT IOUT VOB 1 VOB 2 COLOR
RESET
Resets each block.
8
MB90091A
s ABSOLUTE MAXIMUM RATINGS
(VSS = AVSS = 0 V) Parameter Power supply voltage *1 Input voltage *
2
Symbol VCC AVCC VIN VOUT Pd Ta Tstg
Ratings Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- 0 - 55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 500 + 70 + 150
Unit V V V V mW C C
Output voltage *3 Power consumption Operating temperature Storage temperature
*1: AVCC and VCC must have equal potential. *2: Neither VIN nor VOUT must exceed "VCC + 0.3 V". WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(VSS = AVSS = 0 V) Parameter Power supply voltage * "H" level input voltage "L" level input voltage Operating temperature Analog input voltage Symbol VCC AVCC VIHS1 VIHS2 VILS1 VILS2 Ta VIN Values Min. 4.75 4.75 2.4 0.8 x VCC - 0.3 VSS - 0.3 0 0 Max. 5.25 5.25 VCC + 0.3 VCC + 0.3 0.45 0.2 x VCC + 70 VCC Unit V V V V V V C V FLTOUT input RD0 to RD7 inputs Other inputs RD0 to RD7 inputs Other inputs Remarks Specification guarantee range
* : AVCC and VCC must have equal potential. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with repect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
9
MB90091A
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter "H" level output voltage "L" level output voltage Symbol VOH VOL Pin Conditions VCC = 4.75 V IOH = - 2.0 mA VCC = 4.75 V IOL = 4.0 mA Values Min. 4.0 -- Typ. -- -- Max. -- 0.4 Unit V V
All output pins HSYNC VSYNC EVEN RESET RD0 to RD7 TSEL FSEL SCLK SIN SCS HBLNK VBLNK VCC AVCC
Input current
IIL
VCC = 5.25 V IIL = 4.0 mA
--
--
- 50
mA
Supply current
ICC
VCC = AVCC = 5.25 V DOCK = 42 MHz No load
--
--
40
mA
10
MB90091A
2. AC Characteristics
(1) Serial input timing (VCC = AVCC = 5.0 V 5%, VSS = AVSS = 0 V, Ta = 0C to +70C) Values Symbol Pin Unit Min. Max. tCVC tWCH tWCL tCR tCF tSS tSU tH tEC tCRC tCFC SCLK SCLK SCLK SCLK SIN SIN SCS SCS 1000 450 450 -- -- 200 200 100 500 -- -- -- -- -- 200 200 -- -- -- -- 200 200 ns ns ns ns ns ns ns ns ns ns ns
Parameter Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select end time Chip select signal rise/fall time
SCS
0.8 V CC 0.2 V CC t SS t CFC
0.8 V CC 0.2 V CC t CRC t CYC t EC 0.8 V CC
SCLK t WCH t CR t CF tH t SU 0.8 V CC SIN 0.2 V CC t WCL
0.2 V CC
11
MB90091A
(2) Vertical and horizontal sync signal input timings (VCC = AVCC = 5.0 V 5%, VSS = AVSS = 0 V, Ta = 0C to +70C) Values Symbol Pin Unit Min. Max. tHR tHF tVR tVF tWH tWV tHVST tHVHD HSYNC HSYNC VSYNC VSYNC HSYNC VSYNC VSYNC VSYNC -- -- -- -- 1 2 5 5 200 200 200 200 -- -- -- -- ns ns ns ns s H s s
Parameter Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width Vertical sync signal pulse width Horizontal sync signal setup time Vertical sync signal setup time
HSYNC
0.8 V CC 0.2 V CC t HF t WH
0.8 V CC 0.2 V CC t HR
VSYNC
0.8 V CC 0.2 V CC t VF t WV
0.8 V CC 0.2 V CC t VR
0.8 V CC
HSYNC
t HVST
t HVHD 0.8 V CC 0.2 V CC
VSYNC
12
MB90091A
The MB90091A outputs display signals in synchronization with sync signals input from external circuits. The signals required for controlling synchronization are the horizontal sync signal (input via the HSYNC pin), vertical sync signal (input via the VSYNC pin), and field control signal (input via the EVEN pin). The following examples illustrate external sync signal input timings applicable to general interlaced display. Noninterlaced display does not require the EVEN pin signal.
* External sync signal input timing examples
(1) Field A VSYNC FH (HSYNC) *1 EVEN *2 Slow *2
(2) Field B VSYNC FH (HSYNC) *1 EVEN *2 Fast *2
*1: Input the horizontal sync signal to the HSYNC pin. Input of a composite sync signal may change the FH signal cycle due to the PLL lock disturbed around the VSYNC pulse, requiring a caution to be used for the timing of input to the EVEN pin. (See *2 below.) *2: The input levels of the EVEN pin input signal in fields A and B are determined depending on the relationship between the VSYNC and FH pulse positions. To the EVEN pin, input the "L" level signal in the field in which the FH pulse after the rise of the VSYNC pulse appears fast. Pin the "H" level signal in the field in which it appears slow. The EVEN pin input signal should vary in the undisplay period such as around the VSYNC pulse.
13
MB90091A
(3) RESET signal input timing Parameter Reset input pulse width (VCC = AVCC = 5.0 V 5%, VSS = AVSS = 0 V, Ta = 0C to +70C) Values Symbol Pin Unit Min. Max. tWR RESET 10 -- s
RESET
0.2 V CC t WR 0.2 V CC
14
MB90091A
(4) Address data hold timing Parameter ROM read cycle Address valid delay Address invalid delay Read data setup Read data hold TCS, FCS active delay TCS, FCS inactive delay * : Dot clock = 84 to 42 MHz (VCC = AVCC = 5.0 V 5%, VSS = AVSS = 0 V, Ta = 0C to +70C) Values Symbol Pin Unit Min. Max. trcyc tav tai tds tdh tca tci -- RA0 to RA15 RD0 to RD7 TCS, FCS Dot clock* x 8 -- 0 30 0 -- 0 30 -- -- -- 22 -- -- ns ns ns ns ns ns
t rcyc
8
1
2
3
4
5
6
7
8
1
DOCK
0.2 V CC
RA0 to 15
0.8 V CC 0.2 V CC
t av
t ai 0.8 V CC
TCS, FCS
0.2 V CC
t ci
t ca 0.8 V CC
RD0 to 7
0.2 V CC
t ds
t dh
15
MB90091A
(5) Display data output timing Parameter Symbol (VCC = AVCC = 5.0 V 5%, VSS = AVSS = 0 V, Ta = 0C to +70C) Values Pin Unit Min. Max. ROUT, GOUT, BOUT IOUT, VOB1, VOB2 COLOR 0 22 ns
Display data output delay
t d1
DOCK
0.2 V CC
t d1
ROUT, GOUT, BOUT IOUT, VOB1, VOB2 COLOR
0.8 V CC 0.2 V CC
16
MB90091A
3. Power-on Reset Specifications
(1) Power ON-OFF timing (Ta = 0C to +70C) Parameter Power-supply rise time Power-supply shut-off time Symbol tr VCC, AVCC toff 1 -- ms Pin Values Min. 0.05 Max. 50 Unit ms Remarks Power-on reset circuit activating conditions Conditions in which the circuit repeatedly operate normally
4.75 V
0.2 V
0.2 V
0.2 V
V CC
t
r
t off
Note: The power supply must be activated smoothly
17
MB90091A
(2) Power-on reset cancel timing (Ta = 0C to +70C) Parameter Time after rise Reset cancel pulse width Symbol tWIT tWRH tWRL SCS Pin Values Min. 450 450 450 Max. -- -- -- Unit ns ns ns Power-on reset cancel timing Remarks
4.75 V
V CC
Internal reset
SCS
t WIT 0.8 V CC
SCS
t WRL t CRC* t WRH t CFC*
0.2 V CC
*: See the table in "(1) Serial timing" in Section 2 "AC Characteristics".
18
MB90091A
s Command List
* List of display control commands Command No. First byte Command code/data 76543 10000 10001 10010 10011 10100 10110 10111 7 10111 8 9 10 11 1 0 0 0 0 0 0 0 0 0 0 0 0 -- -- X6 X5 X4 X3 X2 X1 X0 2 0 AT 0 X9 0 SC 0 1 A8 BS M8 X8 0 CC 0 0 A7 B1 M7 X7 0 BC 0 7 0 0 0 0 0 0 0 0 6 A6 BG M6 0 0 W3 ATH Y6 5 A5 BR M5 G2 0 W2 4 A4 BB M4 G1 PC W1 Second byte Data 3 A3 CI M3 G0 PI W0 UI Y3 2 A2 CG M2 PG K24 UG Y2 1 A1 CR M1 PR P0 UR Y1 0 A0 CB M0 PB DC UB Y0 Set write address Set character color Set character code Line control 2 Screen control 1 Screen control 2 Set vertical display start position Set horizontal display start position Set sprite vertical display position Set sprite horizontal display position Function
0 1 2 3 4 5 6
KGR KGD KGU Line control 1
10101 ATK ATR ATB
UC UON Y5 Y4
11000 SP2 SP1 SP0 11001 11010 11011 11011 11100 11100 11101 11101 11110 11111 0 0 0 1 0 1 0 1 -- -- SY8 SY7 SX8 SX7 DOT 0 0 0 0 -- -- 0 1*2 SA7 SAF EA7 -- --
SCG SCR SCB SBP SBG SBR SBB Sprite control SY6 SY5 SY4 SY3 SY2 SY1 SY0 SX6 SX5 SX4 SX3 SX2 SX1 SX0 1*2 0 PR1 PR0 0
SC1 SC0 Synchronization control 1
DK6 DK5 DK4 DK3 DK2 DK1 DK0 Synchronization control 2 SA6 SA5 SA4 SA3 SA2 SA1 SA0*2 Set transfer start address 1 SAE SAD SAC SAB SAA SA9 SA8 Set transfer start address 2 EA6 EA5 EA4 EA3 EA2 EA1 EA0 Set transfer end address 1 EAE EAD EAC EAB EAA EA9 EA8 Set transfer end address 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Reserved) (Reserved)
12 13 14 15
VBS EAF
*1: The SA0 and EA0 bits can only be set to "0" and "1", respectively. *2: Set the bits to "1".
19
MB90091A
1. Command 0 (Set Write Address)
* Command format
MSB First byte 1 MSB Second byte 0 A6 A5 A4 A3 A2 A1 0 0 0 0 0 A8 LSB A7 LSB A0
A8 to A0: VRAM address
* Function Command 0 specifies the write address in display memory (VRAM). Before writing data using commands 1 and 2, use this command to determine the address to write that data at. * Description To set the VRAM address, specify the vertical column address (A8 to A5) and horizontal row address (A4 to A0). The VRAM address is incremented automatically when a character code is set (by command 2). A8 to A0: VRAM address Set the VRAM address. The A8 to A5 bits specify the vertical column address; the A4 to A0 bits specify the horizontal row address. The row address is valid between 00H to 17H. The column address is valid between 0H to BH. Do not set the column or row address to any value outside the above valid range.
20
MB90091A
2. Command 1 (Set Character Color)
* Command format
MSB First byte 1 MSB Second byte AT 0 BG BR BB CI CG CR 0 0 0 1 AT BS LSB BI LSB CB
: Specify character qualification display. (Specify display of a character background, blinking, inverted shading.) : Specify shaded background display. BS B1 to BB : Set a character background color. C1 to CB : Set a character color.
* Function Command 1 sets the character color and character background color and specifies character qualification display and shaded background display. * Description The character color, character background color, character qualification display, and shaded background display can be set/specified for each character. Character background display, blinking, and inverted shading can be used for characters for which character qualification display is specified. These settings are written to VRAM and applied to the display screen the moment command 2 (Set Character Code) is issued. AT: Specify character qualification display. (Specify display of a character background, blinking, inverted shading.) AT = 0: Normal display (without character qualification) This setting suppresses character background display, blinking, and inverted shading in shaded background display. The output level at the VOB2 pin becomes "L". AT = 1: Character qualification display This setting enables character background display, blinking, and inverted shading in shaded background display. "H" level output is enabled at the VOB2 pin. Setting the command 5 (Screen Control 1) ATR bit to "1" specifies character background display. Setting the ATB bit for command 5 (Screen Control 1) to "1" specifies blinking. Setting both the ATK and BS bits for command 5 (Screen Control 1) to "1" specifies inverted shading. Setting the command 6 (Screen Control 2) ATH bit to "1" sets the output level at the VOB2 pin to "H". BS: Specify shaded background display. BS = 0: Normal display (without shaded background display) BS = 1: Shaded background display Setting both the ATK and AT bits for command 5 (Screen Control 1) to "1" specifies inverted shading. C1, CG, CR, CB: Set the character color. B1, BG, BR, BB: Set the background color. 21
MB90091A
3. Command 2 (Set Character Code)
* Command format
MSB First byte 1 MSB Second byte 0 M6 M5 M4 M3 M2 M1 0 0 1 0 0 M8 LSB M7 LSB M0
M8 to M0: Character code
* Function Command 2 writes a character code to display memory (VRAM). * Description The character code data set by this command is written to display memory (VRAM) along with the character color, character background color, shaded background display, and character qualification display data set by command 1 (Set Character Color). Character code is represented by nine bits from M8 to M0, enabling use of 512 different character patterns from 000H to 1FFFH stored in internal or external font ROM. Upon completion of writing data, the write address is incremented automatically. M8 to M0: Character code 000H to 1FFFH can be set to specify 512 different characters.
22
MB90091A
4. Command 3 (Line Control 1)
* Command format
MSB First byte 1 MSB Second byte 0 0 G2 G1 G0 KGR KGD 0 0 1 1 X9 X8 LSB X7 LSB KGU
X9 to X7 : Line horizontal display start position G2 to G0 : Character size : Specify shaded background left/right joint display KGR : Specify shaded background downward joint display KGD : Specify shaded background upward joint display KGU
* Function Command 3 sets the line horizontal display start position, character size, and shaded background joint display for each line. * Description Line control data set by this command is applied to the display screen when command 4 (Line Control 2) is issued. X9 to X7: Line horizontal display start position The offset value can be set for each line, relative to the horizontal display start position set by command 7-1 (Set Horizontal Display Start Position). The valid range of values is 0 to 7H (In 2-character units: 0 to 14 characters)
* Line horizontal display start position
(X6 to X7) (X9, X8, X7) = (0, 0, 0) = (0, 0, 1) = (1, 0, 0) 0 1 2 A 2 characters 8 characters A B C 3 B 4 C 5 D 6 E 7 F 8 G 9 H 1 0 I
23
MB90091A
G2 to G0: Character size G2 0 0 0 0 1 1 1 1 G1 0 0 1 1 0 0 1 1 G0 0 1 0 1 0 1 0 1 Normal Single height x double width Double height x single width Double height x double width Single height x quadruple width (Setting prohibited) Double height x quadruple width (Setting prohibited) Character size
Note: The horizontal display start position for "double width x single or double height" display is shifted three dots to the right from that for normal-size display. The horizontal display start position for "quadruple width x single or double height" display is shifted nine dots to the right from that for normal-size display. Be careful when displaying normal-size and enlarged lines at the same time.
KGR: Specify shaded background left/right joint display. KGR = 0: Display the shaded backgrounds horizontally adjacent to each other, joined together (without display their adjacent, vertical sides). KGR = 1: Display the shaded backgrounds horizontally adjacent to each other, separately for each character (while displaying their adjacent, vertical sides). KGD: Specify shaded background downward joint display. KGD = 0: Display the shaded background including its lower side. KGD = 1: Display the shaded background excluding its lower side. KGU: Specify shaded background upward joint display KGU = 0: Display the shaded background including its lower side. KGU = 1: Display the shaded background excluding its lower side.
24
MB90091A
5. Command 4 (Line Control 2)
* Command format
MSB First byte 1 MSB Second byte 0 0 0 PC PI PG PR 0 1 0 0 0 0 LSB 0 LSB PB
PC : Control the pattern background color. PI to PB : Set the pattern background color.
* Function Command 4 sets the pattern background color and controls it between color and monochrome modes. * Description The data set by this command is written to the column RAM specified by the VRAM column address set by command 0 (Set Write Address), along with the line control data set by command 3 (Line Control 1). The Line Control 1 and 2 data is applied to the display screen and the column address is incremented the moment this command is issued. PC: Control the pattern background color. PC = 0: Display the pattern background in monochrome. During the pattern background color output period, the COLOR pin remains at the "L" output level. PC = 1: Display the pattern background in color. During the pattern background color output period, the COLOR pin remains at the "H" output level. PI, PG, PR, PG: Set the pattern background color.
25
MB90091A
6. Command 5 (Screen Control 1)
* - Command format
MSB First byte 1 MSB Second byte 0 W3 W2 W1 W0 K24 P0 0 1 0 1 ATK ATR
LSB ATB LSB DC
: Control inverted shading. ATK : Control character background display. ATR : Control blinking. ATB W3 to W0 : Control the line spacing. : Specify the shadow frame szize. K24 : Control the pattern background. P0 : Control displ DC
* Function Command 5 controls the display screen. * Description ATK: Control inverted shading. ATK = 0: Normal display Inverted display is disabled. ATK = 1: Enable inverted display. This mode displays those characters in reverse video (with the inverted, shaded background) for which the BS and AT bits for command 1 (Set Character Color) have been both set to "1". ATR: Control character background display. ATR = 0: Normal display Character background display is disabled. ATR = 1: Enable character background display. Character background display applies to those characters for which the BS and AT bits for command 1 (Set Character Color) have been set to "0" and "1", respectively. ATB: Control blinking. ATB = 0: Normal display Blinking is disabled. ATB = 1: Enable blinking. This mode causes those characters to blink for which the AT bit for command 1 (Set Character Color) has been set to "1". W3 to W0: Control the line spacing. Set the line spacing in 2-dot units. 0 to 30 dots can be specified.
26
MB90091A
K24: Specify the shadow frame size. K24 = 0: Set the height of shadow frames for shaded background display to 32 dots. K24 = 1: Set the height of shadow frames for shaded background display to 24 dots. P0: Control the pattern background. P0 = 0: Set pattern background mode "pattern background 0". ROM data "1" is displayed as a character dot. P0 = 1: Set pattern background mode "pattern background 1". Character and pattern background dots are separately generated automatically from a ROM data array. Note: Note: As the pattern background mode, set the mode used when the relevant font was designed. DC: Control display. DC = 0: Disable output operation for displaying characters and sprite characters. Only the screen background color can be output. DC = 0: Enable output operation for displaying characters and sprite characters. The screen background color can also be output.
27
MB90091A
7. Command 6 (Screen Control 2)
* Command format
MSB First byte 1 MSB Second byte 0 ATH UC UON UI UG UR 0 1 1 0 SC CC LSB BC LSB UB
: Control the sprite character color. SC : Control the character color. CC : Control the character background. BC : Control specified character output. ATH : Control the screen background color. UC : Control screen beckground color output. UON UI to UB : Set the screen background color.
* Function Command 6 specifies the character color, character background color, screen background color, sprite character color, color/monochrome mode, specified character output. This command also enables or disables screen background color output and sets the screen background color. * Description SC: Control the sprite character color. SC = 0: Display the sprite character and sprite pattern background in monochrome. During the sprite character/pattern background output period, the COLOR pin outputs the "L" level signal. SC = 1: Display the sprite character and sprite pattern background in color. During the sprite character/pattern background output period, the COLOR pin outputs the "H" level signal. CC: Control the character color. CC = 0: Display characters in monochrome. During the character output period, the COLOR pin outputs the "L" level signal. CC = 1: Display characters in color. During the character output period, the COLOR pin outputs the "H" level signal. BC: Control the character background. BC = 0: Display the character background in monochrome. During the character background output period, the COLOR pin outputs the "L" level signal. BC = 1: Display the character background in color. During the character background output period, the COLOR pin outputs the "H" level signal. Note: Note: Use an external circuit to control display mode between monochrome and color using the COLOR pin.
28
MB90091A
ATH: Control specified character output. ATH = 0: Normal display The VOB2 pin outputs the "L" level signal. ATH = 1: The VOB2 pin outputs the "H" level signal during the output period (24 x 32b dots period) for those characters for which the AT bit for command 1 (Set Character Color) has been set to 1. Note: Note: Use an external circuit to handle the VOB2 pin signal, allowing the specified character to be displayed in halfbright, translucent, and other special display mode. UC: Control the screen background color. UC = 0: Display the screen background in monochrome. During the screen background output period, the COLOR pin outputs the "L" level signal. UC = 1: Display the screen background in color. During the screen background output period, the COLOR pin outputs the "H" level signal. UON: Control screen background color output. UON = 0: Prevent the screen background color from being output. During the screen background color output period, the IOUT, GOUT, ROUT, BOUT, and VOB1 pins output "L" level signals. UON = 1: Output the screen background color. During the screen background color output period, the IOUT, GOUT, ROUT, and BOUT pins output the screen background color and the VOB1 pin outputs the "L" level signal. UI, UG, UR, UB: Set the screen background color.
29
MB90091A
8. Command 7-0 (Set Vertical Display Start Position)
* Command format
MSB First byte 1 MSB Second byte 0 Y6 Y5 Y4 Y3 Y2 Y1 0 1 1 1 0 0
LSB 0 LSB Y0
Y6 to Y0: Set the vertical display start position.
* Function Command 7-0 sets the vertical display start position. * Description Y6 to Y0: Set the vertical display start position. Set the position to start vertical display. The valid range of values is 00H to 7FH for setting in 2-dot units (0 to 254 dots). The following illustrates the relationship between the vertical display start position and the *VSYNC signal.
* Vertical display start position
VSYNC
20H
Vertical display start position
30
MB90091A
9. Command 7-1 (Set Horizontal Display Start Position)
* Command format
MSB First byte 1 MSB Second byte 0 X6 X5 X4 X3 X2 X1 0 1 1 1 1 0
LSB 0 LSB X0
X6 to X0: Set the horizontal display start position.
* Function Command 7-0 sets the horizontal display start position. * Description X6 to X0: Set the horizontal display start position. Set the position to start horizontal display. The valid range of values is 00H to 7FH for setting in 8dot units. The following illustrates the relationship between the horizontal display start position and the YSYNC signal.
* Horizontal display start position
Horizontal operation started* Horizontal display start position
HSYNC
* : Character size: About 100-dot clock for normal display Double or quadruple width display is shifted further to the right from the above value. For details, see Page 24 31
MB90091A
10.Command 8 (Sprite Control)
* Command format
MSB First byte 1 MSB Second byte 0 SCG SCR SCB SBP SBG SBR 1 0 0 0 SP2 SP1 LSB SP0 LSB SBB
SP2 to SP0 : Set sprite character code. SCG to SCB : Set the sprite character color. : Set the sprite pattern background. SBP SBG to SBB : Set the sprite pattern background color.
* Function Command 8 sets the sprite character code, character color, pattern background display, and pattern background color. * Description SP2 to SP0: Set sprite character code. Specify the sprite character type from among character codes 1F8H to 1FFH representing eight character types. SP2 0 0 0 0 1 1 1 1 SP1 0 0 1 1 0 0 1 1 SP0 0 1 0 1 0 1 0 1 Sprite character 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
SCG to SCB: Set the sprite character color. SBP: Control sprite pattern background display. SBP = 0: Display no pattern background for the sprite. This display mode is "No pattern background" (displaying only those character dots displayed in "Pattern background 1" mode). SBP = 1: Display a pattern background for the sprite. This display mode is "Pattern background 1". SBG to SBB: Set the sprite pattern background color.
32
MB90091A
11.Command 9 (Set Sprite Vertical Display Position)
* Command format
MSB First byte 1 MSB Second byte 0 SY6 SY5 SY4 SY3 SY2 SY1 1 0 0 1 0 SY8 LSB SY7 LSB SY0
SY8 to SY0: Set the sprite vertical display position.
* Function Command 9 sets the sprite character vertical display position. * Description SY8 to SY0: Set the sprite vertical display position. Set the vertical display position of the sprite character. The valid range of values is 000H to 1FFH for setting in 2-dot units (0 to 1022 dots). The following illustrates the relationship between the sprite vertical display position and the VSYNC signal.
* Sprite vertical display position
VSYNC
20H
Sprite vertical display position
33
MB90091A
12.Command 10 (Set Sprite Horizontal Display Position)
* Command format
MSB First byte 1 MSB Second byte 0 SX6 SX5 SX4 SX3 SX2 SX1 1 0 1 0 0 SX8 LSB SX7 LSB SX0
SX8 to SX0: Set the sprite horizontal display position.
* Function Command 10 sets the sprite character horizontal display position. * Description SY8 to SY0: Set the sprite horizontal display position. Set the horizontal display position of the sprite character. The valid range of values is 000H to 1FFH for setting in 2-dot units (0 to 1022 dots). Setting these bits to 000H disables sprint display. The following illustrates the relationship between the sprite horizontal display position and the HSYNC signal.
* Sprite horizontal display position
Sprite horizontal display started* Sprite horizontal display position HSYNC
* : About 80-dot clock.
34
MB90091A
13.Command 11-0 (Synchronization Control 1)
* Command format
MSB First byte 1 MSB Second byte 0 1* 0 PR1 PR0 0 SC1 1 0 1 1 0 DOT LSB 0 LSB SC0
: Control dot clock output. DOT PR1, PR0 : Control the prescaler. SC1, SC0 : Control the scan system. *: Set this bit to "1".
* Function Command 10 controls synchronization. * Description DOT: Control dot clock output. DOT = 0: Do not output the dot clock signal to the DOCK pin. DOT = 1: Output the dot clock signal to the dock pin. PR1, PR0: Control the prescaler. PR1 0 0 1 1 PR0 0 1 0 1 Prescaler operation /2 /3 /5 /6 Corresponding dot clock 25.0 to 42.0 MHz 16.7 to 28.3 MHz 10.0 to 17.0 MHz 8.4 to 14.1 MHz
SC1, SC0: Control the scan system. SC1 0 0 1 1 SC2 0 1 0 1 Interlaced scan Noninterlaced scan Step scan (Setting prohibited) Scan system
Interlaced or step scan operation requires the field control signal to be input to the EVEN pin.
35
MB90091A
14.Command 11-1 (Synchronization control 2)
* Command format
MSB First byte 1 MSB Second byte 0 DK6 DK5 DK4 DK3 DK2 DK1 1 0 1 1 1 0 LSB 1* LSB DK0
DK6 to DK0: Control dot clock signals. *: Set this bit to "1".
* Function Command 11-1 controls dot clock signals. * Description DK6 to DK0: Control dot clock signals. Set the divisor in 16-dot units for generating dot clock signals by dividing the FH (horizontal frequency). The valid range of values is 00H to 7FH. This enables the horizontal frequency to be divided by up to 2032.
15.Command 12-0 (Set Transfer Start Address 1)
* Command format
MSB First byte 1 MSB Second byte 0 SA6 SA5 SA4 SA3 SA2 SA1 1 1 0 0 0 0 LSB SA7 LSB SA0*
SA7 to SA0: Lower address for starting transfer from command table ROM *: The SA0 bit can only be set to "0".
* Function Command 12-0 sets the lower address for starting transfer of data from command table ROM. * Description SA7 to SA0: Lower address for starting transfer from command table ROM These bits can be set only to an even address. The SA0 bit is set internally to "0". Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).
36
MB90091A
16.Command 12-1 (Set Transfer Start Address 2)
* Command format
MSB First byte 1 MSB Second byte 0 SAE SAD SAC SAB SAA SA9 1 1 0 0 1 0 LSB SAF LSB SA8
SAF to SA8: Upper address for starting transfer from command table ROM
* Function Command 12-1 sets the upper address for starting transfer of data from command table ROM. * Description SAF to SA8: Upper address for starting transfer from command table ROM Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).
17.Command 13-0 (Set Transfer End Address 1)
* Command format
MSB First byte 1 MSB Second byte 0 EA6 EA5 EA4 EA3 EA2 EA1 1 1 0 1 0 0 LSB EA7 LSB EA0*
EA7 to SA0: Lower address for ending transfer from command table ROM *: The EA0 bit can onlybe set to "1".
* Function Command 13-0 sets the lower address for ending transfer of data from command table ROM. * Description EA7 to EA0: Lower address for ending transfer from command table ROM These bits can be set only to an odd address. The EA0 bit is set internally to "1". Data transfer from ROM is initiated by issuing command 13-1 (Set Transfer End Address 2).
37
MB90091A
18.Command 13-1 (Set Transfer End Address 2)
* Command format
MSB First byte 1 MSB Second byte 0 EAE EAD EAC EAB EAA EA9 1 1 0 1 1 VBS LSB EAF LSB EA8
VBS : Control the ROM transfer period. EAF to EA8 : Upper address for ending transfer from command table ROM
* Function Command 13-1 sets the upper address for ending data transfer from command table ROM and specifies the ROM transfer period to initiate ROM data transfer. * Description VBS: Control the ROM transfer period. VBS = 0: Transfer data during the horizontal and vertical blanking intervals. VBS = 1: Transfer data during the vertical blanking interval. EAF to EA8: Upper address for ending transfer from command table ROM Issuing this command initiates command table ROM transfer operation and sets the TRE pin output to the "H" level. Upon completion of transfer operation, the TRE pin output becomes the "L" level. When the TRE pin output is at the "H" level, do not issue command 0 to 4, 11, 12, or 13 by serial input (commands 5 to 10 can be issued).
38
MB90091A
s APPLICATION EXAMPLES
This section provides useful information for designing application systems using the MB90091A.
1. Power Supply
The MB90091A pairs of digital (VCC, VSS) and analog (AVCC, AVSS) power-supply and ground pins. The VCC and AVCC power-supply pins are independent of each other; the VSS and AVSS ground pins are internally common. Since the analog power supply supplies power and control voltage to the internal VCO, it requires special consideration separately from the digital power supply. In general, pay attention to the following points: * Design the system so that the ground and power supply impedances are suppressed. In addition, the ground line should be laid out on a ground plane including peripheral analog circuits. * The digital (VCC, VSS) and analog (AVCC, AVSS) power supplies must be separated from each other. The VCC and AVCC pins, and the VSS and AVSS pins must not have a potential different in between. * To supply digital and analog power from the same power source, separately route the wires from the source and use a choke coil to prevent digital noise from interfering with the analog subsystem via the power source. * Insert a relatively high-capacity (20 to 100 F) electrolytic capacitor as a bypass capacitor between the power supply and ground, separately between the digital and analog subsystems.
2. Interface with a Microcontroller or Microcomputer
Operation of the MB90091 is controlled by a micro (controller or microcomputer). The MB90091 interfaces with the micro by 8-bit serial transfer using four signal liens as shown below: * Microcontroller/microcomputer interface
Micro Data SO Serial clock TC Chip select Port Internal operation flag Port (or interrupt input) TRE SCS SIN
MB90091A
SCLK
Although most micros can be used for controlling the MB90091A, the one with an 8-bit serial interface (serial port) is recommended because it can be connected directly to the MB90091A for high-speed command/data transfer by means of hardware. (The micro with a 4-bit serial interface can transfer data in two separate blocks.)
Note: Keep in mind that some micros cannot be connected to the serial port depending on the type. Fujitsu 4- and 8-bit microcontrollers have no problem with the MB90091A.
39
MB90091A
3. Treatment of Unused Pins
Pins unused on the MB90091A must be treated as follows. * Treatment of unused pins Pin No. DIP 8 9 10 11 13 15 16 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 38 40 41 42 43 44 45 46 48 49 50 51 52 53 54 55 40 QFP 1 2 3 4 6 8 9 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 Pin name HSYNC VSYNC EVEN FLTIN FLTOUT FH RESET RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 TEST TA16 TA17 TA18 FCS TCS RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 TSEL FSEL SCLK SIN I/O I I I O I O I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O O I I I I Leave the pin open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open. Connect the pin to VSS. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. -- -- -- -- Treatment -- -- Connect the pin to VCC or leave it open. -- --
(Continued)
MB90091A
(Continued) Pin No.
DIP 56 58 59 60 61 62 63 64 1 2 4 5 6 7 QFP 49 51 52 53 54 55 56 57 58 59 61 62 63 64
Pin name SCS TRE ROUT GOUT BOUT IOUT VOB1 VOB2 COLOR DOCK TESTCK TESTSW HBLNK VBLNK
I/O I O O O O O O O O O I I I I Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open. Leave the pin open.
Treatment --
Connect the pin to VCC or leave it open. Connect the pin to VCC. Connect the pin to VCC or leave it open. Connect the pin to VCC or leave it open.
41
MB90091A
s APPLIED CIRCUIT EXAMPLE
MB90091A V CC Sync signal separation 1 2 3 63 64 49 48 47 51 V CC 10 K RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RA10 RA11 RA12 RA13 RA14 RA15 26 27 28 29 31 33 34 35 36 37 38 39 41 42 43 44 HSYNC VSYNC EVEN HBLNK VBLNK SCS SIN SCLK TRE ROUT GOUT BOUT IOUT VOB1 COLOR VOB2 DOCK 52 53 54 55 56 58 57 59 V CC Display control : +5 V (digital)
GND : Ground (digital) AV CC : +5 V (analog) AGND : Grond (analog) This circuit is not required when internal ROM is used. (512-character font ROM) 64K-byte ROM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 OE CE
Micro
46 GND V CC 10 K
FSEL
45 GND NC NC NC GND V CC 62 61 NC V CC
+ -
TSEL
21 22 23 19
O1 O2 O3 O4 O5 O6 O7 O8
TA16 TA17 TA18 TEST
FCS 24
TESTSW TESTCK FH V CC V CC V CC V SS V SS V SS V SS
GND (Command table ROM) 32K-byte ROM A0 A1 A2 A3 A4 A5 A6 O1 A7 O2 A8 O3 A9 O4 A10 O5 A11 O6 A12 O7 A13 O8 A14 TCS 25 OE CE GND
8 10 30 50 20 32 40 60
10
0.1
GND V CC 10 K
+
9 1 GND
RESET
47 GND AV CC 10
+ -
-
0.1
7 5
AV CC AV SS
AGND
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
18 17 16 15 14 13 12 11
6
FLTOUT
FLTIN 4 330 51
+ -
1 AGND
Adjustment is required depending on synchronization system.
42
MB90091A
s ORDERING INFORMATION
Part number MB90091AP MB90091APF Package 64-pin plastic SH-DIP (DIP-64P-M01) 64-pin plastic QFP (FPT-64P-M06) Remarks
43
MB90091A
s PACKAGE DIMENSIONS
64 pin, Plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 +.008 2.283 -.022
+0.22
INDEX-1 INDEX-2
17.000.25 (.669.010)
5.65(.222)MAX 3.00(.118)MIN 1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF
+0.50
0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches).
(Continued)
44
MB90091A
64 pin, Plastic QFP (FPT-64P-M06)
24.700.40(.972.016)
51
3.35(.132)MAX
(Mounting height)
33
20.000.20(.787.008)
0.05(.002)MIN (STAND OFF)
52
32
14.000.20 (.551.008) INDEX
64 20
18.700.40 (.736.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 19
1.00(.0394) TYP
0.400.10 (.016.004)
0.150.05(.006.002) 0.20(.008)
M
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details of "B" part
0 10 1.200.20 (.047.008)
C
1994 FUJITSU LIMITED F64013S-3C-2
Dimensions in mm (inches).
45
MB90091A
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9704 (c) FUJITSU LIMITED
Printed in Japan
48

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